The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 12, 2022

Filed:

Mar. 03, 2021
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventor:

Hideto Takekida, Nagoya Aichi, JP;

Assignee:

KIOXIA CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/24 (2006.01); H01L 27/11556 (2017.01); G11C 16/16 (2006.01); G11C 16/26 (2006.01);
U.S. Cl.
CPC ...
G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/16 (2013.01); G11C 16/24 (2013.01); H01L 27/11556 (2013.01); G11C 16/26 (2013.01);
Abstract

A semiconductor storage device includes a memory string and a row decoder configured to apply voltages to first to fourth select gate lines and first and second word lines connected to the memory string. A sequencer has first mode for erasing the entire memory string and a second mode for erasing just a portion of the memory string. In the first mode, a first voltage is applied to the bit line and the source line, a second voltage lower than the first voltage is applied to the first select gate line, a third voltage is applied to the second select gate line, a fourth voltage is applied to the third select gate line, a fifth voltage lower than the first voltage is applied to the fourth select gate line, and a sixth voltage lower than the first to fifth voltages is applied to the first and second word lines.


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