The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 12, 2022

Filed:

May. 02, 2019
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Peter F. Holland, Los Gatos, CA (US);

Hari Ganesh R. Thirunageswaram, Fremont, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/40 (2006.01); H03K 19/0175 (2006.01); H03K 3/3565 (2006.01); G06F 11/30 (2006.01);
U.S. Cl.
CPC ...
G06F 11/3027 (2013.01); G06F 13/4068 (2013.01); H03K 3/3565 (2013.01); H03K 19/017581 (2013.01);
Abstract

In an embodiment, an integrated circuit includes one or more GPIO pins coupled to a GPIO block in the integrated circuit. At least a first GPIO pin may include corresponding logic circuitry that may be programmed to apply one or more requirements to changes of the digital value received on the first GPIO pin before the change is forwarded to a destination within the integrated circuit. That is, if the requirements are not met for a given change, the logic circuitry may suppress the given change so that it is not provided to other circuits internal to the integrated circuit (e.g. the destination circuit that receives communication via the GPIO pins). The one or more requirements may be a form of hysteresis, for example.


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