The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 12, 2022

Filed:

Sep. 09, 2021
Applicant:

Throughputer, Inc., Williamsburg, VA (US);

Inventor:

Mark Henrik Sandstrom, Alexandria, VA (US);

Assignee:

ThroughPuter, Inc., Williamsburg, VA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/50 (2006.01); G06F 9/48 (2006.01); G06F 8/656 (2018.01); G06F 15/80 (2006.01); H04L 47/78 (2022.01); G06F 15/173 (2006.01);
U.S. Cl.
CPC ...
G06F 9/5038 (2013.01); G06F 9/4881 (2013.01); G06F 8/656 (2018.02); G06F 9/5027 (2013.01); G06F 15/173 (2013.01); G06F 15/80 (2013.01); G06F 2209/483 (2013.01); G06F 2209/5021 (2013.01); H04L 47/78 (2013.01);
Abstract

A configurable logic platform may include a physical interconnect for connecting the platform to a processor, a reconfigurable logic region having logic blocks configured based on configuration data, a configuration port for applying configuration data to the reconfigurable logic region, a reconfiguration logic function accessible via transactions of the physical interconnect and in communication with the configuration port, the reconfiguration logic function providing restricted access to the configuration port from the physical interconnect, and an interface function accessible via transactions of the physical interconnect and providing an interface to the reconfigurable logic region which allows information to be transmitted over the physical interconnect and prevents the reconfigurable logic region from directly accessing the physical interconnect. The reconfiguration logic function may be implemented in the reconfigurable logic region.


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