The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 2022

Filed:

Oct. 31, 2017
Applicant:

Nec Corporation, Tokyo, JP;

Inventors:

Toshinori Araki, Tokyo, JP;

Kazuma Ohara, Tokyo, JP;

Jun Furukawa, Herzliya, IL;

Assignee:

NEC CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 21/00 (2013.01); H04L 9/08 (2006.01); G06F 7/501 (2006.01); G06F 7/72 (2006.01);
U.S. Cl.
CPC ...
H04L 9/085 (2013.01); G06F 7/501 (2013.01); G06F 7/723 (2013.01); H04L 2209/46 (2013.01);
Abstract

A bit-decomposition secure computation apparatus uses r1, r2, and r3 satisfying w=r1+r2+r3 mod 2{circumflex over ( )}n as share information of (2, 3) threshold type RSS (Replicated Secret Sharing) stored in a share value storage apparatus, and includes an addition sharing part that sums two values out of the share information by modulo 2{circumflex over ( )}n arithmetic and distributes the sum using (2, 3) type RSS; and a full adder secure computation part that adds the value generated by the addition sharing part by distributing the sum of the two values to share information of one remaining value other than the two values used by the addition sharing part for each digit by using secure computation of a full adder.


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