The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 2022

Filed:

Sep. 08, 2021
Applicant:

Shanghai Biren Technology Co., Ltd, Shanghai, CN;

Inventors:

Zheng Tian, Shanghai, CN;

YiKai Liang, Shanghai, CN;

Linglan Zhang, Shanghai, CN;

WenQi Li, Shanghai, CN;

DongCai Li, Shanghai, CN;

TingTing Yu, Shanghai, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 23/60 (2006.01); H03K 23/00 (2006.01); H03K 19/08 (2006.01); H03K 19/173 (2006.01); H03K 21/10 (2006.01);
U.S. Cl.
CPC ...
H03K 23/60 (2013.01); H03K 19/0813 (2013.01); H03K 19/1737 (2013.01); H03K 21/10 (2013.01); H03K 23/002 (2013.01);
Abstract

The disclosure provides a clock step control circuit and a method thereof. The clock step control circuit includes a clock divider, a multiplexer, and a controller. The clock divider receives a first clock signal and outputs multiple second clock signals. The multiplexer receives the second clock signals and outputs one of the second clock signals. The controller is coupled to the clock divider and the multiplexer. When the controller receives an interrupt signal, the controller outputs a selection signal to the multiplexer according to the interrupt signal. The multiplexer outputs another one of the second clock signals according to the selection signal. The clock step control circuit and the method thereof in the disclosure can appropriately switch the clock signal to output a clock signal with an appropriate clock frequency.


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