The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 2022

Filed:

Apr. 22, 2020
Applicant:

Murata Manufacturing Co., Ltd., Kyoto, JP;

Inventors:

Hirotsugu Mori, Kyoto, JP;

Hideki Tsukamoto, Kyoto, JP;

Taizo Hisano, Kyoto, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03H 7/46 (2006.01); H03F 3/19 (2006.01); H03H 1/00 (2006.01); H03H 7/01 (2006.01); H03H 7/075 (2006.01); H03H 9/70 (2006.01); H04J 1/02 (2006.01);
U.S. Cl.
CPC ...
H03H 7/46 (2013.01); H03F 3/19 (2013.01); H03H 1/00 (2013.01); H03H 7/0107 (2013.01); H03H 7/0153 (2013.01); H03H 7/075 (2013.01); H03H 9/70 (2013.01); H04J 1/02 (2013.01); H03F 2200/165 (2013.01); H03F 2200/171 (2013.01); H03F 2200/451 (2013.01); H03H 2001/0085 (2013.01);
Abstract

A radio frequency circuit includes a multilayer substrate, series arm circuits in a first path connecting the input/output terminals (Tand T) on the multilayer substrate, a parallel arm circuit in a second path connecting a node on the first path and a ground, a wiring A on the multilayer substrate connected to the input/output terminal (T) as a part of the first path, a wiring B on the multilayer substrate connected to the input/output terminal (T) as a part of the first path, and a wiring C on the multilayer substrate as a part of the second path. The parallel arm circuit includes an impedance variable circuit, the wiring A and the wiring B in a layer different from the multilayer substrate. When viewed in a plan view, the wiring C does not overlap with the wiring A and the wiring B.


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