The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 2022

Filed:

Feb. 27, 2020
Applicants:

Seiko Epson Corporation, Tokyo, JP;

Sophia School Corporation, Tokyo, JP;

Inventors:

Takafumi Noda, Matsumoto, JP;

Katsumi Kishino, Akiruno, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 33/24 (2010.01); H01L 33/18 (2010.01); H01L 27/15 (2006.01); G03B 21/20 (2006.01); H01L 33/40 (2010.01); H01L 33/32 (2010.01); H01L 33/06 (2010.01); H01L 33/00 (2010.01); H01L 33/44 (2010.01); H01L 33/12 (2010.01);
U.S. Cl.
CPC ...
H01L 33/24 (2013.01); G03B 21/2013 (2013.01); G03B 21/2033 (2013.01); H01L 27/153 (2013.01); H01L 33/18 (2013.01); H01L 33/0012 (2013.01); H01L 33/06 (2013.01); H01L 33/12 (2013.01); H01L 33/325 (2013.01); H01L 33/40 (2013.01); H01L 33/44 (2013.01);
Abstract

In a light emitting device, a columnar part includes a first semiconductor layer, a second semiconductor layer different in conductivity type from the first semiconductor layer, and a light emitting layer disposed between the first semiconductor layer and the second semiconductor layer, the first semiconductor layer is disposed between the substrate and the light emitting layer, the light emitting layer includes a first layer, and a second layer larger in bandgap than the first layer, the first semiconductor layer has a facet plane, the first layer has a facet plane, the facet plane of the first semiconductor layer is provided with the first layer, and θ2>θ1, in which θ1 is a tilt angle of the facet plane of the first semiconductor layer with respect to a surface of the substrate provided with the laminated structure, and θ2 is a tilt angle of the facet plane of the first layer provided to the facet plane of the first semiconductor layer with respect to the surface of the substrate.


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