The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 2022

Filed:

Sep. 01, 2020
Applicant:

Kioxia Corporation, Minato-ku, JP;

Inventor:

Masayoshi Tagami, Kuwana, JP;

Assignee:

Kioxia Corporation, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/18 (2006.01); H01L 27/11556 (2017.01); H01L 27/11582 (2017.01);
U.S. Cl.
CPC ...
H01L 24/05 (2013.01); H01L 24/03 (2013.01); H01L 24/06 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 27/11556 (2013.01); H01L 27/11582 (2013.01); H01L 2224/0346 (2013.01); H01L 2224/03612 (2013.01); H01L 2224/03845 (2013.01); H01L 2224/03848 (2013.01); H01L 2224/05018 (2013.01); H01L 2224/05026 (2013.01); H01L 2224/05073 (2013.01); H01L 2224/05186 (2013.01); H01L 2224/05546 (2013.01); H01L 2224/05561 (2013.01); H01L 2224/05567 (2013.01); H01L 2224/05573 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/0616 (2013.01); H01L 2224/06517 (2013.01); H01L 2224/08145 (2013.01); H01L 2924/0537 (2013.01); H01L 2924/0544 (2013.01); H01L 2924/0549 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01);
Abstract

In one embodiment, a semiconductor device includes a substrate, a first interconnection provided above the substrate, and a first pad provided on the first interconnection. The device further includes a second pad provided on the first pad, and a second interconnection provided on the second pad. Furthermore, the first pad includes a first layer provided in a first insulator above the substrate, and a second layer that is provided in the first insulator via the first layer and is in contact with the first interconnection, or the second pad includes a third layer provided in a second insulator above the substrate, and a fourth layer that is provided in the second insulator via the third layer and is in contact with the second interconnection.


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