The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 2022

Filed:

Jan. 13, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Soo-Woong Lee, Seoul, KR;

Doo-Ho Cho, Seoul, KR;

Sang Soo Park, Hwaseong-si, KR;

Yongkyu Lee, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/12 (2006.01); G11C 11/4091 (2006.01); G11C 11/4094 (2006.01); G11C 11/4074 (2006.01); G11C 11/4076 (2006.01); G11C 11/4093 (2006.01); G11C 16/04 (2006.01); G11C 16/34 (2006.01); G11C 16/32 (2006.01); G11C 16/28 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4091 (2013.01); G11C 11/4074 (2013.01); G11C 11/4076 (2013.01); G11C 11/4093 (2013.01); G11C 11/4094 (2013.01); G11C 16/0483 (2013.01); G11C 16/28 (2013.01); G11C 16/32 (2013.01); G11C 16/34 (2013.01); G11C 16/3418 (2013.01);
Abstract

Disclosed is a nonvolatile memory device, which includes a memory cell array that includes a plurality of memory cells, a page buffer circuit that is connected with the memory cell array through a plurality of bit lines and performs a sensing operation of sensing memory cells selected from the plurality of memory cells through the plurality of bit lines during a sensing time, an input/output circuit that performs a data output operation of outputting data from the page buffer circuit to an external device through data lines, and a sensing time control circuit that adjusts the sensing time when the data output operation is performed during the sensing time.


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