The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 2022

Filed:

Aug. 28, 2020
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

Andy Wangkun Chen, Austin, TX (US);

Sriram Thyagarajan, Austin, TX (US);

Yew Keong Chong, Austin, TX (US);

Sony, Noida, IN;

Ettore Amirante, Nice, FR;

Ayush Kulshrestha, New Delhi, IN;

Assignee:

Arm Limited, Cambridge, GB;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/14 (2006.01); G11C 11/4074 (2006.01); G11C 11/4094 (2006.01); G11C 7/10 (2006.01); G11C 11/4091 (2006.01); G11C 11/413 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4074 (2013.01); G11C 5/14 (2013.01); G11C 5/144 (2013.01); G11C 5/146 (2013.01); G11C 7/1012 (2013.01); G11C 11/4091 (2013.01); G11C 11/4094 (2013.01); G11C 11/413 (2013.01);
Abstract

Various implementations described herein are related to a device having memory circuitry with a bitcell array. The device may include a frontside power network that is coupled to the bitcell array, and the device may include a backside power network that provides power to the bitcell array. The device may include transition vias that couple the backside power network to the frontside power network, and the backside power network may provide power to the bitcell array by way of the transition vias being coupled to the frontside power network.


Find Patent Forward Citations

Loading…