Clock driver and memory device comprising the same

Abstract

A clock driver comprises: a clock detector for receiving a plurality pairs of input clock signals of a predetermined clocking protocol, and for generating a protocol identifier indicative of the predetermined clocking protocol; a phase locking loop (PLL) module coupled to receive at least one pair of the plurality pairs of input clock signals, and for generating at least one pair of reference clock signals according to the received at least one pair of input clock signal; and a plurality of multiplexers coupled to the clock detector and to the PLL module. Each multiplexer is configured for receiving one pair of the plurality pairs of input clock signals and one pair of the at least one pair of reference clock signals, and selectively outputting, according to the protocol identifier, the pair of input clock signals and the pair of reference clock signals to drive a group of memory chips.