The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 2022

Filed:

May. 06, 2019
Applicant:

Bfly Operations, Inc., Guilford, CT (US);

Inventors:

Kailiang Chen, Branford, CT (US);

Nevada J. Sanchez, Guilford, CT (US);

Susan A. Alie, Stoneham, MA (US);

Tyler S. Ralston, Clinton, CT (US);

Jonathan M. Rothberg, Miami Beach, FL (US);

Keith G. Fife, Palo Alto, CA (US);

Joseph Lutsky, Los Altos, CA (US);

Assignee:

BFLY Operations, Inc., Guilford, CT (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04B 1/06 (2006.01); A61B 8/08 (2006.01); H04B 11/00 (2006.01); A61B 8/00 (2006.01);
U.S. Cl.
CPC ...
A61B 8/5207 (2013.01); A61B 8/4483 (2013.01); A61B 8/54 (2013.01); H04B 11/00 (2013.01);
Abstract

Aspects of the technology described herein relate to an ultrasound device including a first die that includes an ultrasonic transducer, a first application-specific integrated circuit (ASIC) that is bonded to the first die and includes a pulser, and a second ASIC in communication with the second ASIC that includes integrated digital receive circuitry. In some embodiments, the first ASIC may be bonded to the second ASIC and the second ASIC may include analog processing circuitry and an analog-to-digital converter. In such embodiments, the second ASIC may include a through-silicon via (TSV) facilitating communication between the first ASIC and the second ASIC. In some embodiments, SERDES circuitry facilitates communication between the first ASIC and the second ASIC and the first ASIC includes analog processing circuitry and an analog-to-digital converter. In some embodiments, the technology node of the first ASIC is different from the technology node of the second ASIC.


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