The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 28, 2022

Filed:

May. 07, 2018
Applicant:

Brillnics Singapore Pte. Ltd., Singapore, SG;

Inventor:

Toshinori Otaka, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04N 5/374 (2011.01); H04N 5/3745 (2011.01); H04N 5/369 (2011.01); H04N 5/345 (2011.01); H04N 5/378 (2011.01);
U.S. Cl.
CPC ...
H04N 5/37452 (2013.01); H04N 5/3454 (2013.01); H04N 5/3698 (2013.01); H04N 5/378 (2013.01); H04N 5/379 (2018.08); H04N 5/3741 (2013.01);
Abstract

In a solid-state imaging device, a signal retaining partis provided with a first sampling partand a second sampling part, each of which is formed by one sampling transistor (1T) and one sampling capacitor (1C). The coupling node between the two sampling parts is a retaining node ND, which is used as a bidirectional port. With such a configuration, the solid-state imaging deviceis configured as a solid-state imaging element having a global shutter function that achieves substantially the same signal amplitude as in the differential reading scheme with four transistors. Thus, the solid-state imaging devicecan achieve the reduced increase in number of transistors, prevent the occurrence of signal amplitude loss in the sampling parts, maintain high pixel sensitivity and reduce input conversion noise.


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