The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 28, 2022

Filed:

Nov. 28, 2019
Applicant:

Stmicroelectronics (Rousset) Sas, Rousset, FR;

Inventors:

Nicolas Borrel, Gardanne, FR;

Jimmy Fort, Puyloubier, FR;

Mathieu Lisart, Aix en Provence, FR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/22 (2006.01); H03K 19/003 (2006.01); H03K 19/00 (2006.01); H03K 19/17736 (2020.01); H03F 3/45 (2006.01); H03L 7/097 (2006.01); H04L 9/32 (2006.01);
U.S. Cl.
CPC ...
H03K 19/00384 (2013.01); H03F 3/45273 (2013.01); H03F 3/45488 (2013.01); H03K 19/0027 (2013.01); H03K 19/17744 (2013.01); H03L 7/097 (2013.01); H04L 9/3278 (2013.01); H04L 2209/12 (2013.01);
Abstract

The physically unclonable function device (DIS) comprises a set of MOS transistors (TR, TR) mounted in diodes having a random distribution of respective threshold voltages, and comprising N first transistors and at least one second transistor. At least one output node of the function is capable of delivering a signal, the level of which depends on the comparison between a current obtained using a current circulating in the at least one second transistor and a current obtained using a reference current that is equal or substantially equal to the average of the currents circulating in the N first transistors. A first means (FM) is configured to impose on each first transistor a respective fixed gate voltage regardless of the value of the current circulating in the first transistor, and a second means (SM) is configured to impose a respective fixed gate voltage on each second transistor regardless of the value of the current circulating in the second transistor.


Find Patent Forward Citations

Loading…