The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 28, 2022

Filed:

Oct. 09, 2020
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Prashant Dubey, Greater Noida, IN;

Sundeep Ram Gopal Agarwal, Hyderabad, IN;

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/528 (2006.01); H01L 25/065 (2006.01); H03K 17/687 (2006.01); H01L 27/06 (2006.01);
U.S. Cl.
CPC ...
H03K 17/6871 (2013.01); H01L 23/481 (2013.01); H01L 23/5286 (2013.01); H01L 25/0657 (2013.01); H01L 27/0688 (2013.01); H01L 2225/06541 (2013.01);
Abstract

Examples of the present disclosure provide power gating for stacked die structures. In some examples, a stacked die structure comprises a first die and a second die bonded to the first die. In some examples, a power gated power path is from a bonding interface between the dies through TSVs in the second die, a power gating device in the second die, and routing of metallization layers in the second die to the circuit region in the second die. In some examples, a power gated power path comprises a power gating device in a power gating region of the first die and is configured to interrupt a flow of current through the power gated power path to a circuit region in the second die.


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