The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 28, 2022

Filed:

Feb. 27, 2019
Applicant:

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Ming Yang, Beijing, CN;

Minghua Xuan, Beijing, CN;

Can Zhang, Beijing, CN;

Can Wang, Beijing, CN;

Han Yue, Beijing, CN;

Ning Cong, Beijing, CN;

Jiayao Liu, Beijing, CN;

Wenqing Zhao, Beijing, CN;

Li Xiao, Beijing, CN;

Dongni Liu, Beijing, CN;

Lei Wang, Beijing, CN;

Liang Chen, Beijing, CN;

Xiaochuan Chen, Beijing, CN;

Shengji Yang, Beijing, CN;

Pengcheng Lu, Beijing, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1362 (2006.01); G02F 1/1343 (2006.01); G02F 1/1368 (2006.01); H01L 27/12 (2006.01); G02B 30/26 (2020.01); G02F 1/1335 (2006.01); H01L 27/32 (2006.01); G09G 3/3266 (2016.01); G09G 3/3275 (2016.01); G09G 3/36 (2006.01);
U.S. Cl.
CPC ...
H01L 27/124 (2013.01); G02B 30/26 (2020.01); G02F 1/1368 (2013.01); G02F 1/13439 (2013.01); G02F 1/133526 (2013.01); G02F 1/136286 (2013.01); H01L 27/3276 (2013.01); G02F 2201/123 (2013.01); G09G 3/3266 (2013.01); G09G 3/3275 (2013.01); G09G 3/3677 (2013.01); G09G 3/3688 (2013.01); G09G 2300/0426 (2013.01); G09G 2310/0205 (2013.01); G09G 2310/0297 (2013.01);
Abstract

There is provided an array substrate including a plurality of pixel regions arranged in rows and columns. The plurality of pixel regions include a corresponding pixel electrode array and a corresponding pixel circuit associated with the corresponding pixel electrode array. Each of the pixel electrode arrays is arranged in rows and columns, and each pixel electrode array includes a plurality of pixel electrodes arranged in an array. The array substrate further includes a plurality of sets of gate lines extending in a row direction and a plurality of sets of data lines extending in a column direction. The plurality of sets of gate lines and rows of the pixel electrode arrays are alternately arranged with each other in the column direction. The plurality of sets of data lines and columns of the pixel regions are alternately arranged with each other in the row direction.


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