The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 28, 2022

Filed:

Apr. 04, 2018
Applicant:

Commissariat À L'energie Atomique ET Aux Energies Alternatives, Paris, FR;

Inventor:

Umberto Rossini, Coublevie, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); G09G 3/32 (2016.01); H05K 3/12 (2006.01); H05K 3/46 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0655 (2013.01); G09G 3/32 (2013.01); H05K 3/125 (2013.01); H05K 3/1216 (2013.01); H05K 3/465 (2013.01); H05K 3/4664 (2013.01); G09G 2310/0297 (2013.01);
Abstract

The invention concerns a display device including a transfer substrate () including electric connection elements (L, L, C, C, P, P, P, P), and a plurality of semiconductor chips, wherein the transfer substrate () includes an insulating plate, the electric connection elements of the substrate being formed by printing, on a surface of said plate, of a first conductive level, followed by an insulating level, followed by a second conductive level, the electric connection elements of the substrate including: a plurality of first conductive tracks (L, L) formed in the first conductive level; a plurality of second conductive tracks (C, C) formed in the second conductive level; and for each chip of the device, a plurality of electric connection areas (P, P, P, P) respectively connected to connection terminals of the chip, said areas being all formed in the second conductive level.


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