The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 28, 2022

Filed:

Jan. 28, 2021
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Sung Hyun Hwang, Gyeonggi-do, KR;

Jin Haeng Lee, Gyeonggi-do, KR;

Assignee:

SK hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/34 (2006.01); G11C 16/14 (2006.01); G11C 16/30 (2006.01); G11C 11/56 (2006.01); G11C 16/10 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3459 (2013.01); G11C 11/56 (2013.01); G11C 16/10 (2013.01); G11C 16/14 (2013.01); G11C 16/30 (2013.01); G11C 16/0483 (2013.01);
Abstract

Provided herein may be a memory device and a method of operating the same. The memory device may include a plurality of memory cells, each having an erased state or any one of a plurality of program states, a peripheral circuit configured to perform a program operation including a plurality of program loops, and an operation controller configured to control the peripheral circuit so that, in response to a pass in verification for an N-th program state among the plurality of program states in a verify phase included in an x-th program loop among the plurality of program loops, verification for an N+M-th program state among the plurality of program states starts in a verify phase included in an x+1-th program loop among the plurality of program loops.


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