The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 28, 2022

Filed:

Nov. 24, 2020
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Ali Rabbani Rankouhi, St Albans, GB;

Christopher A. Burns, Bushey, GB;

Justin A. Hensley, Mountain View, CA (US);

Luca Iuliano, Milton Keynes, GB;

Jonathan M. Redshaw, St Albans, GB;

Assignee:

Apple Inc., Cupertino, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06T 15/06 (2011.01); G06T 1/20 (2006.01); G06T 15/00 (2011.01); G06F 9/48 (2006.01); G06F 9/50 (2006.01); G06F 16/22 (2019.01); G06F 30/31 (2020.01); G06T 17/10 (2006.01); G16H 40/67 (2018.01); G06Q 10/10 (2012.01); G06Q 50/04 (2012.01);
U.S. Cl.
CPC ...
G06T 15/06 (2013.01); G06F 9/4881 (2013.01); G06F 9/5027 (2013.01); G06F 16/2246 (2019.01); G06F 30/31 (2020.01); G06T 1/20 (2013.01); G06T 15/005 (2013.01); G06Q 10/101 (2013.01); G06Q 50/04 (2013.01); G06T 17/10 (2013.01); G06T 2210/12 (2013.01); G06T 2210/21 (2013.01); G16H 40/67 (2018.01);
Abstract

Disclosed techniques relate to grouping rays during traversal of a spatially-organized acceleration data structure (e.g., a bounding volume hierarchy) for ray intersection processing. The grouping may provide temporal locality for accesses to bounding region data. In some embodiments, ray intersect circuitry is configured to group rays based on the node of the data structure that they target next. The ray intersect circuitry may select one or more groups of rays for issuance each clock cycle, e.g., to bounding region test circuitry.


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