The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 28, 2022

Filed:

Oct. 12, 2021
Applicant:

Classiq Technologies Ltd., Tel Aviv, IL;

Inventors:

Amir Naveh, Haifa, IL;

Shmuel Ur, Shorashim, IL;

Yehuda Naveh, Tel-Aviv Yafo, IL;

Ofek Kirzner, Haifa, IL;

Ravid Alon, Tel Aviv, IL;

Tal Goren, Kibbutz Nahsholim, IL;

Adam Goldfeld, Kiryat Motzkin, IL;

Nir Minerbi, Haifa, IL;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 10/00 (2022.01); G06N 5/00 (2006.01);
U.S. Cl.
CPC ...
G06N 10/00 (2019.01); G06N 5/003 (2013.01);
Abstract

A method, system and product comprising: obtaining a directed acyclic graph representing a quantum circuit, the directed acyclic graph comprising a set of blocks and connections therebetween, wherein a connection between a first block and a second block indicates passing an output value of a qubit outputted by the first block to be an input value of a qubit manipulated by the second block; determining a Constraint Satisfaction Problem (CSP) based on the directed acyclic graph, wherein the CSP comprises one or more constraints based on the connections defined by the directed acyclic graph; automatically solving the CSP, wherein said automatically solving comprises selecting an implementation to each block that adheres to the one or more constraints; and synthesizing a gate-level representation of the quantum circuit based on the solution to the CSP.


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