The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 28, 2022
Filed:
Jan. 25, 2021
Applicant:
SK Hynix Inc., Icheon-si, KR;
Inventors:
Seung Wook Oh, Icheon-si, KR;
Chang Hyun Kim, Icheon-si, KR;
Young Jae An, Icheon-si, KR;
Woong Rae Kim, Icheon-si, KR;
Assignee:
SK hynix Inc., Icheon-si, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G06F 3/06 (2006.01); G11C 7/10 (2006.01); G11C 7/20 (2006.01); G11C 8/10 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0659 (2013.01); G06F 3/0604 (2013.01); G06F 3/0673 (2013.01); G11C 7/106 (2013.01); G11C 7/1066 (2013.01); G11C 7/1069 (2013.01); G11C 7/1096 (2013.01); G11C 7/20 (2013.01); G11C 8/10 (2013.01); G11C 2207/2272 (2013.01);
Abstract
A semiconductor system includes a memory controller and a memory apparatus. The memory controller provides at least first to third command address signals. The memory apparatus performs a burst read operation based on the first and second command address signals, and terminates the burst read operation by receiving the third command address signal twice. The memory apparatus continuously initializes an internal circuit that is performing the burst read operation in a section the third command address signal is received twice.