The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 28, 2022

Filed:

Nov. 20, 2020
Applicant:

Microsoft Technology Licensing, Llc, Redmond, WA (US);

Inventors:

Taylor Alan Hope, Redmond, WA (US);

Vinod R Shankar, Redmond, WA (US);

Justin Sing Tong Cheung, Redmond, WA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0619 (2013.01); G06F 3/065 (2013.01); G06F 3/067 (2013.01); G06F 3/0631 (2013.01); G06F 3/0653 (2013.01); G06F 3/0659 (2013.01); G06F 3/0683 (2013.01);
Abstract

A data storage array is configured for m-way resiliency across a first plurality of storage nodes. The m-way resiliency causes the data storage array to direct each top-level write to at least m storage nodes within the first plurality, for committing data to a corresponding capacity region allocated on each storage node to which each write operation is directed. Based on the data storage array being configured for m-way resiliency, an extra-resilient cache is allocated across a second plurality of storage nodes comprising at least s storage nodes (where s>m), including allocating a corresponding cache region on each of the second plurality for use by the extra-resilient cache. Based on determining that a particular top-level write has not been acknowledged by at least n of the first plurality of storage nodes (where n m), the particular top-level write is redirected to the extra-resilient cache.


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