The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 28, 2022

Filed:

Mar. 25, 2019
Applicant:

Nordic Semiconductor Asa, Trondheim, NO;

Inventors:

Adrian J. Anderson, Chepstow, GB;

Gary C. Wass, St. Albans, GB;

Gareth J. Davies, Kings Langley, GB;

Assignee:

Nordic Semiconductor ASA, Trondheim, NO;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/54 (2006.01); G06F 9/30 (2018.01); G06F 9/50 (2006.01); G06F 12/1081 (2016.01); G06F 3/06 (2006.01); G06F 13/28 (2006.01); G06F 9/38 (2018.01);
U.S. Cl.
CPC ...
G06F 3/0607 (2013.01); G06F 3/0629 (2013.01); G06F 3/0658 (2013.01); G06F 3/0673 (2013.01); G06F 9/3009 (2013.01); G06F 9/3851 (2013.01); G06F 9/5016 (2013.01); G06F 9/542 (2013.01); G06F 9/544 (2013.01); G06F 12/1081 (2013.01); G06F 13/28 (2013.01); G06F 2212/251 (2013.01);
Abstract

A technique for transferring data in a digital signal processing system is described. In one example, the digital signal processing system comprises a number of fixed function accelerators, each connected to a memory access controller and each configured to read data from a memory device, perform one or more operations on the data, and write data to the memory device. To avoid hardwiring the fixed function accelerators together, and to provide a configurable digital signal processing system, a multi-threaded processor controls the transfer of data between the fixed function accelerators and the memory. Each processor thread is allocated to a memory access channel, and the threads are configured to detect an occurrence of an event and, responsive to this, control the memory access controller to enable a selected fixed function accelerator to read data from or write data to the memory device via its memory access channel.


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