Key management device and processor chip having bypass channels

Abstract

A key management device for data encryption/decryption is provided. The key management device includes a static random access memory (SRAM), a register, an arbitration circuit, and a control circuit. The arbitration circuit is electrically connected to an encryption/decryption device having a plurality of encryption/decryption circuits. There is a bypass channel between each encryption/decryption circuit and the arbitration circuit. The control circuit arranges a key lookup table in the SRAM or the register, and manages a key database including the SRAM and a one-time programmable memory. The key lookup table includes a key number and metadata of each key stored in the key database. In response to the control circuit retrieving a specific key corresponding to a specific key number indicated by a key read command, the control circuit directly transmits the retrieved specific key to the corresponding encryption/decryption circuit through the corresponding bypass channel.