The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 21, 2022

Filed:

Sep. 05, 2018
Applicant:

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Zhaohui Qiang, Beijing, CN;

Jianhua Du, Beijing, CN;

Feng Guan, Beijing, CN;

Chunhao Li, Beijing, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78618 (2013.01); H01L 27/127 (2013.01); H01L 27/1222 (2013.01); H01L 27/1229 (2013.01); H01L 27/1274 (2013.01); H01L 27/1285 (2013.01); H01L 29/78696 (2013.01);
Abstract

The present disclosure provides a thin film transistor, a fabricating method thereof, an array substrate, and a display device. The thin film transistor includes: a substrate; a channel region; a heavily doped first semiconductor pattern located on both sides of the channel region; a second semiconductor pattern disposed on the heavily doped first semiconductor pattern; a gate insulating layer covering the channel region and the second semiconductor pattern; a gate pattern disposed on the gate insulating layer, an orthographic projection of the gate pattern on the substrate being within an orthographic projection of the channel region on the substrate; and a source pattern and a drain pattern in contact with the heavily doped first semiconductor pattern through the first via and the second via, respectively.


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