The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 21, 2022
Filed:
Aug. 14, 2020
Applicant:
Cerebras Systems Inc., Los Altos, CA (US);
Inventors:
Jean-Philippe Fricker, Los Altos, CA (US);
Philip Ferolito, Los Altos, CA (US);
Assignee:
Cerebras Systems Inc., Los Altos, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 25/065 (2006.01); H01L 23/00 (2006.01); H01L 23/58 (2006.01); H01L 21/48 (2006.01);
U.S. Cl.
CPC ...
H01L 23/538 (2013.01); H01L 21/4889 (2013.01); H01L 23/5386 (2013.01); H01L 23/562 (2013.01); H01L 23/564 (2013.01); H01L 23/585 (2013.01); H01L 24/43 (2013.01); H01L 24/48 (2013.01); H01L 24/94 (2013.01); H01L 25/0655 (2013.01); H01L 2224/48137 (2013.01);
Abstract
A semiconductor and a method of fabricating the semiconductor having multiple, interconnected die including: providing a semiconductor substrate having a plurality of disparate die formed within the semiconductor substrate, and a plurality of scribe lines formed between pairs of adjacent die of the plurality of disparate die; and fabricating, by a lithography system, a plurality of inter-die connections that extend between adjacent pair of die of the plurality of die.