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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11367665 B1

PDFFull Text
Date of Patent:
Jun. 21, 2022

Filed:

Jul. 24, 2018

Precision structured glass articles, integrated circuit packages, optical devices, microfluidic devices, and methods for making the same

Applicant:

Corning Incorporated, Corning, NY (US);

Inventors:

Heather Debra Boek, Corning, NY (US);

Paul Bennett Dohn, Corning, NY (US);

Jin Su Kim, Seoul, KR;

Aize Li, Painted Post, NY (US);

Hugh Michael McMahon, Millport, NY (US);

Jun Ro Yoon, Painted Post, NY (US);

Assignee:

CORNING INCORPORATED, Corning, NY (US);

Attorney:

Daniel J. Greenhalgh

Primary Examiner:

Luan C Thai

Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 23/13 (2006.01); B32B 17/06 (2006.01); B81B 1/00 (2006.01); C03C 3/087 (2006.01); C03C 3/091 (2006.01); C03C 3/093 (2006.01); C03C 3/097 (2006.01); C03C 15/00 (2006.01); H01L 21/48 (2006.01); H01L 23/15 (2006.01); H01L 23/498 (2006.01); C03C 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/13 (2013.01); B32B 17/06 (2013.01); B81B 1/002 (2013.01); C03C 3/087 (2013.01); C03C 3/091 (2013.01); C03C 3/093 (2013.01); C03C 3/097 (2013.01); C03C 15/00 (2013.01); H01L 21/4846 (2013.01); H01L 23/15 (2013.01); H01L 23/49816 (2013.01); H01L 23/49838 (2013.01); B32B 2310/0409 (2013.01); B32B 2310/0831 (2013.01); B32B 2315/08 (2013.01); B32B 2457/14 (2013.01); B81B 2203/0315 (2013.01); C03C 23/002 (2013.01); C03C 23/007 (2013.01);
Abstract

The present disclosure relates to a reconstituted wafer- and/or panel-level package comprising a glass substrate having a plurality of cavities. Each cavity is configured to hold a single IC chip. The reconstituted wafer- and/or panel-level package can be used in a fan-out wafer or panel level packaging process. The glass substrate can include at least two layers having different photosensitivities with one layer being sufficiently photosensitive to be capable of being photomachined to form the cavities.

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