The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 21, 2022
Filed:
May. 25, 2021
Cypress Semiconductor Corporation, San Jose, CA (US);
Venkataraman Prabhakar, Pleasanton, CA (US);
Krishnaswamy Ramkumar, San Jose, CA (US);
Vineet Agrawal, San Jose, CA (US);
Long Hinh, San Jose, CA (US);
Swatilekha Saha, San Jose, CA (US);
Santanu Kumar Samanta, West Bengal, IN;
Michael Amundson, Woodinville, WA (US);
Ravindra M. Kapre, San Jose, CA (US);
Infineon Technologies LLC, San Jose, CA (US);
Abstract
A semiconductor inference device that has a non-volatile memory (NVM) array including NVM cells arranged in rows and columns, in which each NVM cell comprises a charge trapping transistor configured to store one of N×analog values corresponding to N×levels of its drain current (ID) or threshold voltage (VT) levels, representing N×weight values for multiply accumulate (MAC) operations. The semiconductor inference device also includes digital-to-analog (DAC) function and multiplexor (mux) function configured to generate an analog MAC result based on the digital inputs converted results and the weight values read results, and analog-to-digital (ADC) function configured to convert the analog MAC result of the mux function to a digital value. Other embodiments of the semiconductor inference device and related methods and systems are also disclosed.