The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 21, 2022

Filed:

Nov. 25, 2020
Applicant:

Marvell Asia Pte, Ltd., Singapore, SG;

Inventor:

Michael ThaiThanh Phan, Cary, NC (US);

Assignee:

MARVELL ASIA PTE, LTD., Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/412 (2006.01); G11C 11/418 (2006.01); G11C 11/419 (2006.01); G06F 12/0893 (2016.01); G11C 7/10 (2006.01); G06F 12/0895 (2016.01); G06F 12/0897 (2016.01); G11C 8/16 (2006.01); G11C 7/12 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); G06F 12/0893 (2013.01); G11C 11/412 (2013.01); G11C 11/418 (2013.01); G06F 12/0895 (2013.01); G06F 12/0897 (2013.01); G06F 2212/1028 (2013.01); G06F 2212/603 (2013.01); G11C 7/1045 (2013.01); G11C 7/1069 (2013.01); G11C 7/1096 (2013.01); G11C 7/12 (2013.01); G11C 8/16 (2013.01);
Abstract

A memory device provides for a multiple-port read operation, and includes an array of bitcells and a control circuit. Each bitcell of the array includes a write wordline port and a first read wordline port. The control circuit provides an output to the write wordline port, and includes as inputs a write select port and a second read wordline port. In a write mode, the control circuit couples the write select port to the output and disables the second read port. In a read mode, the control circuit couples the second read wordline port to the output and disables the write select port, thereby enabling a multiple-port read operation to the array of bitcells.


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