The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 14, 2022

Filed:

Jul. 09, 2019
Applicant:

Csem Centre Suisse D'electronique ET DE Microtechnique Sa—recherche ET Développement, Neuchâtel, CH;

Inventors:

Pascal Heim, St. Aubin, CH;

Pierre-François Rüedi, Marin, CH;

Riccardo Quaglia, Neuchâtel, CH;

Engin Türetken, Ecublens, CH;

Pascal Nussbaum, Fontainemelon, CH;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 5/369 (2011.01); H04N 5/355 (2011.01); H04N 5/3745 (2011.01); H04N 5/378 (2011.01);
U.S. Cl.
CPC ...
H04N 5/3698 (2013.01); H04N 5/355 (2013.01); H04N 5/378 (2013.01); H04N 5/37452 (2013.01);
Abstract

A pixel circuit for a ultra-low power image sensor, including: an integration node, on which a photodiode current is integrated, a comparator arranged to compare a voltage at the integration node with a reference voltage, a n+1 bits digital memory, a writing pulse signal generator arranged to generate a writing pulse signal, on the basis of the comparator output voltage and on the voltage at a memory node, the start of the pulse triggering the writing of the digital word in the n-bits digital memory part. The comparator includes a switch in series with a current source and arranged to be commanded by the voltage at the memory node so that the switch is open at the end of the pulse, so as to drastically limit the consumption of static power of the pixel circuit during the integration phase.


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