The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 14, 2022
Filed:
Dec. 13, 2018
No.24 Research Institute of China Electronics Technology Group Corporation, Chongqing, CN;
Tao Liu, Chongqing, CN;
Jian'an Wang, Chongqing, CN;
Yuxin Wang, Chongqing, CN;
Guangbing Chen, Chongqing, CN;
Dongbing Fu, Chongqing, CN;
Ruzhang Li, Chongqing, CN;
Shengdong Hu, Chongqing, CN;
Zhengping Zhang, Chongqing, CN;
Jun Luo, Chongqing, CN;
Daiguo Xu, Chongqing, CN;
Minming Deng, Chongqing, CN;
Yan Wang, Chongqing, CN;
Abstract
The present disclosure provides a low-jitter frequency division clock circuit, including: a clock control signal generation circuit, to generate clock signals having different phases; a low-level narrow pulse width clock control signal generation circuit, to generate a low-level narrow pulse width clock control signal; a high-level narrow pulse width clock control signal generation circuit, to generate a high-level narrow pulse width clock control signal; and a frequency division clock generation circuit, to generate a frequency division clock signal according to low-level narrow pulse width clock control signal and high-level narrow pulse width clock control signal. The delay from a clock input end to an output end of low-jitter frequency division clock circuit is up to three logic gates. Compared with traditional divide-by-2 frequency division clock circuits based on D-flip-flop, the low-jitter frequency division clock circuit of the present disclosure has fewer logic gates, a shorter delay, and lower jitter.