The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 14, 2022

Filed:

Dec. 10, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Aroma Bhat, Bengaluru, IN;

Abdur Rakheeb, Bengaluru, IN;

Arani Roy, Bengaluru, IN;

Mitesh Goyal, Bengaluru, IN;

Abhishek Ghosh, Bengaluru, IN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/3562 (2006.01); G01R 31/3177 (2006.01); H03K 3/027 (2006.01); H03K 3/012 (2006.01);
U.S. Cl.
CPC ...
H03K 3/35625 (2013.01); G01R 31/3177 (2013.01); H03K 3/012 (2013.01); H03K 3/027 (2013.01);
Abstract

A pre-discharging based flip-flop having a negative setup time can include a flip-flop with an inverted output QN. The flip-flop includes a master section and a slave section. The master section latches a data input or a scan input signal based on a scan enable signal, and the slave section retains a previous value of the inverted output QN when a clock signal is at a low logic level. The master section retains a previously latched value of the data input or the scan input signal and the slave section fetches the latched value of the master section and provides a new inverted output QN when the clock signal is at a high logic level. Further, the master section includes sub-sections that are operated using a negative clock signal. An output of the master section is discharged to zero for a half of a phase of the clock cycle.


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