The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 14, 2022

Filed:

Sep. 30, 2020
Applicant:

AU Optronics Corporation, Hsinchu, TW;

Inventor:

Jia-Hong Ye, New Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 21/02 (2006.01); H01L 27/12 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7869 (2013.01); H01L 21/02164 (2013.01); H01L 21/02271 (2013.01); H01L 21/02532 (2013.01); H01L 21/02565 (2013.01); H01L 21/02631 (2013.01); H01L 21/02675 (2013.01); H01L 27/1225 (2013.01); H01L 27/1274 (2013.01); H01L 29/42364 (2013.01); H01L 29/42384 (2013.01); H01L 29/4908 (2013.01); H01L 29/66765 (2013.01); H01L 29/66969 (2013.01); H01L 29/78633 (2013.01); H01L 29/78678 (2013.01);
Abstract

An active device substrate includes a substrate, a first active device, and a second active device. The first active device includes a first gate, a crystallized metal oxide layer, a first insulation layer, a first source, and a first drain. The crystallized metal oxide layer is located on the first gate. The first insulation layer is sandwiched between the crystallized metal oxide layer and the first gate. An area from the top surface of the crystallized metal oxide layer to the bottom surface of the crystallized metal oxide layer is observed via a selected area diffraction mode of a transmission electron microscope, and a diffraction pattern of a crystallized phase can be observed. The second active device includes a second gate, a silicon semiconductor layer, a second source, and a second drain. A manufacturing method of an active device substrate is further provided.


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