The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 14, 2022
Filed:
Mar. 22, 2019
Ordos Yuansheng Optoelectronics Co., Ltd., Inner Mongolia, CN;
Boe Technology Group Co., Ltd., Beijing, CN;
Zhixuan Guo, Beijing, CN;
Fengguo Wang, Beijing, CN;
Yezhou Fang, Beijing, CN;
Feng Li, Beijing, CN;
Xinguo Wu, Beijing, CN;
Hong Liu, Beijing, CN;
Zifeng Wang, Beijing, CN;
Lei Li, Beijing, CN;
Kai Li, Beijing, CN;
Liang Tian, Beijing, CN;
Jing Zhao, Beijing, CN;
Zhengkui Wang, Beijing, CN;
Bo Ma, Beijing, CN;
Haiqin Liang, Beijing, CN;
Peng Liu, Beijing, CN;
Ordos Yuansheng Optoelectronics Co., Ltd., Inner Mongolia, CN;
BOE Technology Group Co., Ltd., Beijing, CN;
Abstract
The present disclosure relates to the technical field of display. Disclosed are an array substrate and a preparation method therefor, and a display panel and a display device. The array substrate includes: a substrate; multiple gate lines, wherein the gate lines are located on the substrate, and extend along a first direction; multiple data lines, wherein the data lines are located on the substrate, and extend along a second direction, and the gate lines and the data lines intersect to define multiple pixel areas; and a touch-control electrode wiring wherein the touch-control electrode wiring has the same direction as that of the gate lines, and is arranged insulated from the gate lines on a different layer, and the orthographic projection of the touch-control electrode wiring on the substrate at least has an overlapping area with the orthographic projection of part of the gate lines on the substrate.