The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 14, 2022

Filed:

Jan. 08, 2020
Applicant:

Hitachi Energy Switzerland Ag, Baden, CH;

Inventors:

Dominik Trüssel, Bremgarten, CH;

Samuel Hartmann, Staufen, CH;

David Guillon, Vorderthal, CH;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/08 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/14 (2006.01); H01L 23/29 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/08 (2013.01); H01L 21/481 (2013.01); H01L 21/565 (2013.01); H01L 23/142 (2013.01); H01L 23/29 (2013.01); H01L 23/3178 (2013.01);
Abstract

The present invention provides a power semiconductor module, including a substrate having an electric insulating main layer being provided with a structured top metallization and with a bottom metallization, wherein the top metallization is provided with at least one power semiconductor device and at least one contact area, wherein the main layer together with its top metallization and the at least one power semiconductor device is embedded in a mold compound such that the mold compound includes at least one opening for contacting the at least one contact area, and wherein power semiconductor module includes a housing with circumferential side walls, wherein the side walls are positioned above the main layer of the substrate so that the side walls are only present in a space above a plane through the main layer of the substrate.


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