The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 14, 2022

Filed:

Mar. 26, 2020
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Satoshi Inoue, Kanagawa, JP;

Daisuke Arizono, Kanagawa, JP;

Assignee:

KIOXIA CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/06 (2006.01); G11C 7/10 (2006.01); G11C 16/26 (2006.01); G11C 11/00 (2006.01); G11C 7/04 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G11C 16/06 (2013.01); G11C 7/10 (2013.01); G11C 7/1057 (2013.01); G11C 7/1084 (2013.01); G11C 16/26 (2013.01); G11C 7/04 (2013.01); G11C 11/00 (2013.01); G11C 16/0483 (2013.01); G11C 2207/2254 (2013.01);
Abstract

A method for controlling a memory system, including a controller chip and a non-volatile memory chip which includes a calibration control circuit, a first output buffer, and a first resistance element, includes receiving a read command from the controller, setting a ready/busy signal to a busy state based on the read command, executing a calibration operation which controls an impedance of the first output buffer based on the read command, setting the ready/busy signal to a ready state, and sending data to the control chip in response to the read command. The calibration control circuit calibrates the impedance of the first output buffer circuit by using the first resistance element within a period in which the ready/busy signal is the busy state.


Find Patent Forward Citations

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Inoue, Satoshi. (2022). Semiconductor memory device having bonded first and second semiconductor chips provided with respective impedance calibration control circuits (U.S. Patent No. 11361823). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11361823

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