The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 14, 2022

Filed:

Aug. 25, 2020
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Arun Babu Pallerla, San Diego, CA (US);

Changho Jung, San Diego, CA (US);

Sung Son, San Jose, CA (US);

Jason Cheng, San Diego, CA (US);

Yandong Gao, San Diego, CA (US);

Chulmin Jung, San Diego, CA (US);

Venugopal Boynapalli, San Diego, CA (US);

Assignee:

QUALCOMM INCORPORATED, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 11/4096 (2006.01); G11C 11/408 (2006.01); G11C 5/02 (2006.01); G11C 11/4074 (2006.01); G11C 11/4094 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4096 (2013.01); G11C 5/025 (2013.01); G11C 11/4074 (2013.01); G11C 11/4085 (2013.01); G11C 11/4094 (2013.01);
Abstract

A bitcell architecture for a pseudo-triple-port memory is provided that includes a a bitcell arranged on a semiconductor substrate, the bitcell defining a bitcell width and a bitcell height and including a first access transistor and a second access transistor. A first metal layer adjacent the semiconductor substrate is patterned to form a pair of local bit lines arranged within the bitcell width. The pair of local bit lines includes a local bit line coupled to a terminal of the first access transistor and includes a complement local bit line coupled to a terminal of the second access transistor.


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