The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 14, 2022

Filed:

Aug. 18, 2020
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Zhixin Cui, Nagoya, JP;

Rajdeep Gautam, Yokohama, JP;

Hardwell Chibvongodze, Hiratsuka, JP;

Assignee:

SanDisk Technologies LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/4094 (2006.01); G11C 11/4093 (2006.01); G11C 5/02 (2006.01); G11C 11/408 (2006.01); G11C 11/4074 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4094 (2013.01); G11C 5/025 (2013.01); G11C 11/4074 (2013.01); G11C 11/4085 (2013.01); G11C 11/4093 (2013.01);
Abstract

Apparatuses and techniques are described for providing separate source regions in the substrate below a block of memory cells. The source regions can be separately driven by respective voltage drivers to provide benefits such as more uniform program and erase speeds and narrower threshold voltage distributions. In one approach, a single source region is provided and divided into multiple source regions by etching trenches and filling the trenches with an insulating material. Contacts to the source regions can include post-shaped contacts which extend through the block for each source region. In another approach, one or more planar contacts extend through the block for each source region. In another aspect, a program operation applies different voltages to the respective source regions during a verify test of a program operation.


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