The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 14, 2022

Filed:

Jan. 08, 2021
Applicant:

Aspiring Sky Co. Limited, Hong Kong, CN;

Inventors:

Zhijiong Luo, Hopewell Township, PA (US);

Xuntong Zhao, Shanghai, CN;

Assignee:

Aspiring Sky Co. Limited, Hong Kong, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 14/00 (2006.01); G11C 11/408 (2006.01); G11C 5/02 (2006.01); G11C 7/12 (2006.01); G11C 7/18 (2006.01); G11C 8/08 (2006.01); G11C 11/419 (2006.01); G06F 12/02 (2006.01); G06F 12/06 (2006.01); G06F 13/16 (2006.01); G11C 8/10 (2006.01); G11C 11/418 (2006.01); G11C 16/08 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4085 (2013.01); G06F 12/0246 (2013.01); G06F 12/0638 (2013.01); G06F 13/1694 (2013.01); G11C 5/025 (2013.01); G11C 7/12 (2013.01); G11C 7/18 (2013.01); G11C 8/08 (2013.01); G11C 8/10 (2013.01); G11C 11/419 (2013.01); G11C 14/0063 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1028 (2013.01); G06F 2212/205 (2013.01); G06F 2212/7203 (2013.01); G11C 11/418 (2013.01); G11C 14/00 (2013.01); G11C 16/08 (2013.01); Y02D 10/00 (2018.01);
Abstract

Technologies for a three-dimensional (3D) multi-bit non-volatile dynamic random access memory (nvDRAM) device, which may include a DRAM array having a plurality of DRAM cells with single or dual transistor implementation and a non-volatile memory (NVM) array having a plurality of NVM cells with single or dual transistor implementations, where the DRAM array and the NVM array are arranged by rows of word lines and columns of bit lines. The nvDRAM device may also include one or more of isolation devices coupled between the DRAM array and the NVM array and configured to control connection between the dynamic random access bit lines (BLs) and the non-volatile BLs. The word lines run horizontally and may enable to select one word of memory data, whereas bit lines run vertically and may be connected to storage cells of different memory address.


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