The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 14, 2022
Filed:
Oct. 26, 2021
AU Optronics Corporation, Hsin-Chu, TW;
Che-Wei Tung, Hsin-Chu, TW;
Shang-Jie Wu, Hsin-Chu, TW;
Yu-Chieh Kuo, Hsin-Chu, TW;
Yu-Hsun Chiu, Hsin-Chu, TW;
Che-Chia Chang, Hsin-Chu, TW;
Yu-Zuo Lin, Hsin-Chu, TW;
Chen-Ying Chou, Hsin-Chu, TW;
Yi-Fan Chen, Hsin-Chu, TW;
AU OPTRONICS CORPORATION, Hsin-Chu, TW;
Abstract
The present disclosure relates to a driving circuit including a pulse amplitude modulation (PAM) circuit and a pulse width modulation (PWM) circuit. The PAM circuit includes a first transistor, a first capacitor, and a second transistor. The PWM circuit includes a second capacitor, a third transistor, and a fourth transistor. The first capacitor's first terminal is connected to the first transistor's gate. The second transistor's first terminal is connected to the first capacitor's first terminal, and the second transistor's second terminal is connected to the first transistor's second terminal. The third transistor's gate is connected to the second capacitor's second terminal. The fourth transistor's first terminal is connected to the third transistor's gate, the fourth transistor's second terminal is connected to the third transistor's second terminal, and the fourth transistor's gate is connected to the second transistor's gate and configured to receive a first control signal.