The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 14, 2022

Filed:

Aug. 31, 2020
Applicant:

Siemens Industry Software Inc., Plano, TX (US);

Inventor:

Joel Cooper, Saskatoon, CA;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/30 (2020.01); G06F 30/398 (2020.01); G06F 119/18 (2020.01); G06F 119/02 (2020.01);
U.S. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 2119/02 (2020.01); G06F 2119/18 (2020.01);
Abstract

A computing system can implement a circuit verification tool to perform scaled sampling of parameter values in a foundry model describing parameter variations for a manufacturing process capable of fabricating an integrated circuit described in a circuit design. The computing system can simulate the circuit design with the scaled samples of the parameter values, and build a geometric model to describe a response of the circuit design to the scaled samples of the parameter values during the simulation. The geometric model can include one or more failure regions corresponding to geometric descriptions for failures of the circuit design to meet a specification during simulation with the scaled samples of the parameter values. The computing system can estimate a yield for an output of the integrated circuit described by the circuit design based on the failure regions in the geometric model.


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