Two-dimensional data matching method, device and logic circuit

Abstract

Provided are a two-dimensional data matching method, a device and a logic circuit. The method is executed by a first operator, a first queue, a second operator, a first counter, a second queue, a third operator, a second counter, a first comparator, and a first memory sequentially connected. The method includes: the first operator performs a bitwise matching operation on the matrix a and the matrix b row by row, inputting the result to the first queue; the second operator performs a cumulative operation on the matching result, and outputting an accumulative value to the second queue; the second operator performs a cumulative operation on the accumulative value, and inputs an accumulated result to the first comparator; the first comparator compares the accumulated result with a pre-stored matching threshold, and inputs the comparison result to the first memory to form a matching result matrix; and repeating the above steps.