The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2022

Filed:

Aug. 26, 2019
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Sunil M. Akre, Santa Clara, CA (US);

Kejiu Zhang, Los Gatos, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/16 (2006.01); H05K 1/02 (2006.01); H05K 1/18 (2006.01); H01F 27/28 (2006.01); H01F 27/24 (2006.01); H01F 41/04 (2006.01); H05K 3/30 (2006.01); H01F 27/40 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0263 (2013.01); H01F 27/24 (2013.01); H01F 27/2804 (2013.01); H01F 27/40 (2013.01); H01F 41/041 (2013.01); H05K 1/0203 (2013.01); H05K 1/165 (2013.01); H05K 1/185 (2013.01); H05K 3/30 (2013.01); H01F 2027/2809 (2013.01); H05K 2201/066 (2013.01); H05K 2201/10015 (2013.01); H05K 2201/10053 (2013.01);
Abstract

The disclosed technology relates to a power supply circuit that utilizes an integrated power module that has a first and second power converter disposed on opposite sides of an inductor core. The power supply circuit includes an inductor core comprising a plurality of nano-magnetic layers embedded within a printed circuit board, a first winding disposed on a first outer surface of the inductor core, a second winding disposed on a second outer surface of the inductor core, a first active layer disposed on an outer surface of the first winding, a second active layer disposed on an outer surface of the second winding, a first capacitor tile disposed on an outer surface of the first active layer, and a second capacitor tile disposed on an outer surface of the second active layer.


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