The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2022

Filed:

Dec. 03, 2020
Applicant:

Shenzhen Goodix Technology Co., Ltd., Shenzhen, CN;

Inventor:
Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/085 (2006.01); H04B 5/00 (2006.01); G06K 19/07 (2006.01); H04W 4/80 (2018.01); G06K 19/073 (2006.01); H03L 7/08 (2006.01); H04L 7/00 (2006.01);
U.S. Cl.
CPC ...
H04B 5/0062 (2013.01); G06K 19/073 (2013.01); G06K 19/0723 (2013.01); H03L 7/08 (2013.01); H03L 7/085 (2013.01); H04B 5/0031 (2013.01); H04B 5/0068 (2013.01); H04L 7/00 (2013.01); H04W 4/80 (2018.02);
Abstract

Techniques are described for accurate tracking of a radiofrequency (RF) carrier for amplitude-modulated signals in unstable reference clock environments. For example, some embodiments operate in context of clock circuits in devices configured for near-field communication (NFC) card emulation (CE) mode. The clock circuits seek to generate an internal clocking signal by tracking a clock reference, such as an RF carrier. In some cases, the clock reference can unpredictably become unreliable for periods of time, during which continued tracking of the unreliable clock reference and/or improper reacquisition can yield appreciable frequency and phase errors in the generated internal clocking signal. Some embodiments implement phase delta detection with time limiting to limit the magnitude of such errors in the internal clocking signal introduced while tracking an unreliable clock reference. Other embodiments provide feedback-pause-control (FPC) to force proper clock reference reacquisition. Such FPC can be implemented additionally with time-limited phase detection.


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