The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2022

Filed:

Feb. 11, 2021
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Michael Douglas Seeman, San Jose, CA (US);

Sandeep R. Bahl, Palo Alto, CA (US);

David I. Anderson, Saratoga, CA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/08 (2006.01); H03K 17/082 (2006.01); H03K 17/10 (2006.01); H02H 3/00 (2006.01); H03K 3/012 (2006.01); H03K 17/687 (2006.01);
U.S. Cl.
CPC ...
H03K 17/0822 (2013.01); H02H 3/00 (2013.01); H03K 3/012 (2013.01); H03K 17/08 (2013.01); H03K 17/102 (2013.01); H03K 2017/0806 (2013.01); H03K 2017/6875 (2013.01);
Abstract

In described examples, a first transistor has: a drain coupled to a source of a depletion-mode transistor; a source coupled to a first voltage node; and a gate coupled to a control node. A second transistor has: a drain coupled to a gate of the depletion-mode transistor; a source coupled to the first voltage node; and a gate coupled through at least one first logic device to an input node. A third transistor has: a drain coupled to the gate of the depletion-mode transistor; a source coupled to a second voltage node; and a gate coupled through at least one second logic device to the input node.


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