The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2022

Filed:

Mar. 06, 2020
Applicant:

Brookhaven Science Associates, Llc, Upton, NY (US);

Inventors:

Charles T. Black, New York, NY (US);

Mingzhao Liu, Syosset, NY (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 39/22 (2006.01); H01L 39/24 (2006.01); B82Y 40/00 (2011.01); G06N 10/00 (2022.01); B82Y 10/00 (2011.01); H01L 39/02 (2006.01);
U.S. Cl.
CPC ...
H01L 39/223 (2013.01); B82Y 10/00 (2013.01); B82Y 40/00 (2013.01); G06N 10/00 (2019.01); H01L 39/025 (2013.01); H01L 39/2493 (2013.01);
Abstract

A qubit device for use in a quantum computing environment includes a semiconductor substrate, an insulating layer disposed on at least a portion of an upper surface of the substrate, and a transition metal silicide (TMSi) heterojunction disposed on at least a portion of an upper surface of the insulating layer. The TMSi heterojunction includes a link layer and at least first and second TMSi regions coupled with the link layer. The link layer may include a normal conductor, thereby forming a superconductor-normal conductor-superconductor (SNS) junction, or a geometric constriction, thereby forming a superconductor-geometric constriction-superconductor (ScS) junction. The link layer may form at least a portion of a channel including intrinsic or doped silicon.


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