The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2022

Filed:

May. 01, 2019
Applicant:

Stanley Electric Co., Ltd., Tokyo, JP;

Inventor:

Akihiko Hanya, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 33/62 (2010.01); H01L 23/528 (2006.01); H01L 23/522 (2006.01); H05K 3/12 (2006.01); H05K 1/09 (2006.01); H01L 33/00 (2010.01); H01L 33/52 (2010.01);
U.S. Cl.
CPC ...
H01L 33/62 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 33/005 (2013.01); H01L 33/52 (2013.01); H05K 1/097 (2013.01); H05K 3/12 (2013.01); H05K 3/1283 (2013.01);
Abstract

An aspect of the invention provides a multilayer circuit substrate that has a simple configuration and is thin. The multilayer circuit substrate has a stacked multiple of substrates and a wiring pattern disposed so to be sandwiched between the stacked multiple of substrates. At least one portion of the wiring pattern is configured of a conductive material wherein conductive particles are sintered. An upper face of the wiring pattern is directly joined to the substrate positioned above the wiring pattern, a lower face of the wiring pattern is directly joined to the substrate positioned below the wiring pattern, and the stacked multiple of substrates are fixed to each other by the wiring pattern.


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