The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2022

Filed:

Nov. 24, 2020
Applicant:

Imec Vzw, Leuven, BE;

Inventors:

Abhitosh Vais, Heverlee, BE;

Liesbeth Witters, Lubbeek, BE;

Yves Mols, Wijnegem, BE;

Assignee:

IMEC VZW, Leuven, BE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/08 (2006.01); H01L 29/737 (2006.01); H01L 21/306 (2006.01); H01L 29/205 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66318 (2013.01); H01L 29/0826 (2013.01); H01L 29/7371 (2013.01); H01L 21/30612 (2013.01); H01L 29/205 (2013.01);
Abstract

A method for fabricating a heterojunction bipolar transistor (HBT) comprises providing a semiconductor support layer and forming an even number of at least four elongated wall structures on the support layer. The wall structures are arranged side-by-side at a regular interval. An odd number of at least three semiconductor collector-material ridge structures are formed on the support layer. Each ridge structure is formed between two adjacent wall structures. A semiconductor base-material layer is formed on a determined ridge structure of the at least three ridge structures. A semiconductor emitter-material layer is formed on the base-material layer. The base-material layer is epitaxially extended so that it coherently covers all the wall structures and all the ridge structures. All the ridge structures except for the determined ridge structure are selectively removed.


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