The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 07, 2022
Filed:
Jun. 28, 2018
Applicant:
Western Digital Technologies, Inc., San Jose, CA (US);
Inventors:
Nir Amir, Beit Hashmonai, IL;
Avichay Hodes, Kfar Ben Nun, IL;
Assignee:
Western Digital Technologies, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01); G01R 31/28 (2006.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01); H01L 25/065 (2006.01); G01R 31/3185 (2006.01);
U.S. Cl.
CPC ...
H01L 22/32 (2013.01); G01R 31/2886 (2013.01); G01R 31/2896 (2013.01); G01R 31/318597 (2013.01); H01L 23/3107 (2013.01); H01L 23/481 (2013.01); H01L 23/49816 (2013.01); H01L 25/0652 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/06562 (2013.01);
Abstract
A semiconductor device includes through-package debug features enabling debug of a BGA package while mounted to a printed circuit board or other host device. In one example, the through-package debug features are filled or plated vias extending from a surface of the semiconductor device, through a device housing, down to test pads on the substrate. In another example, the through-package debug features are open channels formed from a surface of the semiconductor device.