The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2022

Filed:

Mar. 05, 2020
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Keith Edmund Kunz, Tucson, AZ (US);

Joseph Alan Sankman, Dallas, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G05F 1/46 (2006.01); G11C 27/02 (2006.01); G05F 3/26 (2006.01); G01R 19/165 (2006.01); H03K 5/24 (2006.01); H03K 19/21 (2006.01); G05F 1/575 (2006.01); G05F 1/613 (2006.01);
U.S. Cl.
CPC ...
G11C 27/026 (2013.01); G01R 19/16552 (2013.01); G05F 1/468 (2013.01); G05F 1/575 (2013.01); G05F 1/613 (2013.01); G05F 3/262 (2013.01); H03K 5/24 (2013.01); H03K 19/21 (2013.01);
Abstract

A system includes an input voltage source, a linear regulator coupled to the input voltage source, and a load coupled to an output of the linear regulator. The linear regulator includes an error amplifier coupled to a control terminal of a switch; and a control circuit coupled to the error amplifier and configured to provide a reference voltage to the error amplifier. The control circuit includes a mode selection circuit with a slow loop configured to sample a load current and with a fast loop configured to detect an output voltage error signal. The mode selection circuit is configured to adjust a mode of the control circuit between a continuous power mode and a duty cycle power save mode based on the sampled load current and the output voltage error signal.


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